Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole&#39;s upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.11/610,899, filed Dec. 14, 2006, which claims the benefit of KoreanPatent Application No. 10-2005-0129865, filed Dec. 26, 2005, which areincorporated herein by reference in their entirety.

FIELD OF INVENTION

The present invention relates to a semiconductor device and a method formanufacturing the same.

BACKGROUND OF THE INVENTION

In general, there has been a rapid change toward high performance innext generation semiconductor devices. As a result, a via hole size hasbecome reduced and the aspect ratio thereof has become increased. Thus,superior step coverage, via filling capability and high speed operationof a device has become necessary. To this end, a method for forming ametal interconnection on a damascene pattern using copper has beensuggested as a useful method. As an example of conventional methods forforming copper interconnection, there is a method including the steps offorming a diffusion barrier layer and a seed layer for forming copperthrough physical vapor deposition, forming a copper interconnectionlayer on the seed layer through electroplating to fill a via with thecopper interconnection, and performing chemical mechanical polishing.FIGS. 1 to 3 are sectional views representing a method for forming ametal interconnection of a semiconductor device according to the relatedart.

First, referring to FIG. 1, after an interlayer dielectric layer 30 isformed on a semiconductor substrate 10 having a conductive layer 20thereon, a hole 40 is formed by partially etching the interlayerdielectric layer 30.

Then, referring to FIG. 2, a diffusion barrier layer 50 and a seed layer60 including copper are sequentially stacked in the hole 40 and on thesurface of the interlayer dielectric layer 30.

In detail, the seed layer 60 and the diffusion barrier layer 50 areformed through a PVD (Plasma Vapor Deposition) process. However, areduction of the via size and an increase of the step difference maycause a poor step coverage, so that overhang A or a depositiondiscontinuous point B may occur.

Referring to FIG. 3, a copper interconnection layer 70 is deposited onthe seed layer 60 through electroplating so as to fill the hole 40.

However, a void C is formed in the hole 40 due to the overhang A and thedeposition discontinuous point B. As described above, according to therelated art, the overhang, the deposition discontinuous point and voidscause the increase of the contact resistance so that the reliability ofthe semiconductor device is reduced.

Further, according to the related art, such overhang, depositiondiscontinuous point and voids may become serious problems because theaspect ratio of the hole may increase as the degree of integration ofthe semiconductor device increases.

BRIEF SUMMARY

Embodiments of the present invention can solve the above problemsoccurring in the prior art. An embodiment of the present invention canprovide a semiconductor device and a method for manufacturing the same,capable of preventing an overhang or a void from being generated due toa step difference in the process of forming a diffusion barrier layerand a seed layer.

Another embodiment of the present invention is to provide asemiconductor device and a method for manufacturing the same, capable ofpreventing the performance degradation of the semiconductor devicecaused by an overhang or a void, thereby preventing the reliability ofthe semiconductor device from being degraded.

To achieve the above, embodiments of the present invention provide asemiconductor device comprising: a semiconductor substrate having aconductive layer; an interlayer dielectric layer formed on thesemiconductor substrate and provided with a hole having a tapered angleon the upper portion; a diffusion barrier layer formed on the hole andthe interlayer dielectric layer; and a seed layer formed on thediffusion barrier layer.

Another aspect of the present invention provides a method comprising:forming an interlayer dielectric layer on the semiconductor substratehaving a conductive layer; forming a first photoresist layer having apredetermined thickness on the interlayer dielectric layer; exposing anentire surface of the first photoresist layer; forming a shielding layeron the exposed first photoresist layer; forming and patterning a secondphotoresist layer on the shielding layer; etching the shielding layerexposed by the patterned second photoresist layer; developing andremoving a predetermined portion of the first photoresist layer which isexposed by the etched shielding layer; and forming a hole by etching theinterlayer dielectric layer exposed by the removal of the predeterminedportion of the first photoresist layer.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 to 3 are sectional views illustrating a method for forming ametal interconnection of a semiconductor device according to the relatedart; and

FIGS. 4 to 12 are sectional views illustrating a method formanufacturing a semiconductor device according to an exemplaryembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter a semiconductor device and a method for manufacturing thesame according to an exemplary embodiment of the present invention willbe explained in detail with reference to accompanying drawings.

In the following description the expression “formed on each layer” mayinclude the meaning of both “formed directly on each layer” and “formedindirectly on each layer”.

FIGS. 4 to 12 illustrate a method for forming a metal interconnection ofa semiconductor device in accordance with an exemplary embodiment of thepresent invention.

Referring to FIG. 4 an interlayer dielectric layer 120 is formed on asemiconductor substrate 100 where a conductive layer 110 is formed.

Then referring to FIG. 5, a photoresist is coated on the interlayerdielectric layer 120 to a predetermined thickness so as to form a firstphotoresist layer 130. The first photoresist layer 130 can have athickness such that the width of the undercut portion can be controlled.

In a specific embodiment, the first photoresist layer 130 can have athickness within a range of about 50 nm to about 200 nm. That is, whenthe thickness of the first photoresist layer 130 is less than 50 nm, anundercut hardly occurs, and when the thickness of the first photoresistlayer 130 exceeds 200 nm, the undercut excessively occurs so that ataper angle of the interlayer dielectric layer 120 is excessivelyincreased.

For instance, according to an embodiment of the present embodiment, anundercut having a proper size may be obtained by forming the firstphotoresist layer 130 with a thickness of about 100 nm.

Subsequently, a blank exposure process can be performed to expose theentire surface of the first photoresist layer 130) to light withoutusing a photo mask.

Then, referring to FIG. 6, a shielding layer 140 can be formed on thefirst photoresist layer 130.

The shielding layer 140 functions to protect the first photoresist layer130 except for the regions of the first photoresist layer 130 exposed ina subsequent process from making contact with a developer.

In one embodiment a middle metal layer formed by depositing a metal canbe used as the shielding layer 140. However, the present invention isnot limited thereto. That is, in other embodiments, an insulating layersuch as an oxide layer or a nitride layer can be used as the shieldinglayer 140.

The middle metal layer 140 can be deposited through PVD (Physical VaporDeposition) or CVD (Chemical Vapor Deposition).

In a specific embodiment, the middle metal layer 140 can be aluminumdeposited on the first photoresist layer 130 through CVD.

The middle metal layer 140 can Support a second photoresist layer 150,described below, and serves as a mask when removing the firstphotoresist layer 130.

Referring to FIG. 7, a second photoresist layer 150 can be formed on themiddle metal layer 140 and patterned for forming a trench.

For example, the second photoresist layer 150 can be exposed to lightthrough a predetermined photo mask so that the second photoresist layer150 is patterned on the middle metal layer 140. Accordingly, apredetermined portion of the middle metal layer 140 is exposed.

Then, referring to FIG. 8, the exposed middle metal layer 140 can beetched so that a predetermined portion of the first photoresist layer130 is exposed.

In this case, a wet etching process or a dry etching process can be usedas a method for etching the middle metal layer 140.

In one embodiment, the exposed middle metal layer 140 can be etchedthrough RIE (Reactive Ion Etch).

A predetermined portion of the first photoresist layer 130 positionedunder the middle metal layer 140 is exposed as the predetermined portionof the middle metal layer 140 is removed.

Then, referring to FIG. 9, the exposed first photoresist layer 130 canbe developed.

Since the first photoresist layer 130 is blank-exposed in the previousprocess, the undercut, which is sunk in at a predetermined angle andremoved, may occur as the exposed portion of the first photoresist layer130 is developed.

As the first photoresist layer 130 has been partially undercut, overhangcan be prevented from being generated in the following process offorming the diffusion barrier layer 170 and the seed layer 180.

Referring to FIG. 10, as the exposed portion of the first photoresistlayer 130 is removed, a predetermined portion of the interlayerdielectric layer 120 can be exposed. The exposed portion of theinterlayer dielectric layer 120 can be etched so as to form a hole 160for the interconnection between layers. Accordingly, a predeterminedportion of the conductive layer 110 is exposed.

The hole 160 can be formed as a trench a via hole or a contact holedepending on the desired application.

In an embodiment, a wet etching process or a dry etching process can beused for etching the interlayer dielectric layer 120. The interlayerdielectric layer 120 can be etched such that the hole 160 is formedtherein, and the upper portion thereof is sunk at a predetermined angle.

In this case, the upper portion of the hole 160 has a width wider thanthe width of the lower portion of the hole 160.

If the interlayer dielectric layer 120 is etched through the dry etchingprocess, the lower portion of the hole 160 can have a width identical toa width of a middle portion of the hole 160, and the upper portion ofthe hole can have a width wider than the width of the lower portion ofthe hole.

That is, according to the exemplary embodiment of the present invention,since the lower portion of the first photoresist layer 130 formed on theinterlayer dielectric layer 120 is undercut to be sunk at apredetermined angle, the etching rate may increase at the upper portionof the interlayer dielectric layer 120. Accordingly, after the etchingprocess has been performed, the hole 160 is formed in the interlayerdielectric layer 120 and the upper portion of the interlayer dielectriclayer 120 is sunk at a predetermined angle.

The upper portion of the interlayer dielectric layer 120 and the lowerportion of the first photoresist layer 130, being sunk in atpredetermined angles, form sink parts 161.

Referring to FIG. 11, the first photoresist layer 130, the middle metallayer 140 and the second photoresist layer 150 can be removed leaving ahole 160 in the interlayer dielectric layer 120 having a tapered angleat the upper portion of the hole 160.

Referring to FIG. 12, a diffusion barrier layer 170 and a seed layer 180can be sequentially stacked on the interlayer dielectric layer 120.

The diffusion barrier layer 170 prevents a metal interconnection layerto be filled in the hole in the following process from diffusing intothe interlayer dielectric layer 120, and the seed layer 180 acceleratesthe growth of the metal interconnection layer.

In detail, the diffusion barrier layer 170 can be formed on theinterlayer dielectric layer 120 and the exposed portion of theconductive layer 110, and the seed layer 180 can be formed on thediffusion barrier layer 170.

The diffusion barrier layer 170 may be formed of a single TaN layer, asingle Ta layer, or a dual TaN/Ta layer.

Referring to FIG. 12, the diffusion barrier layer 170 may include a duallayer of TaN/Ta 171 and 172.

Since the upper portion of the interlayer dielectric layer 120 ischamfered at a predetermined angle, the diffusion barrier layer 170 andthe seed layer formed on the interlayer dielectric layer 120 are alsochamfered at a predetermined angle.

Accordingly, the overhang does not occur in the process of forming thediffusion barrier layer 170 and the seed layer 180 so a void which maygenerate in the metal interconnection layer to be filled in the hole 160can be prevented. After forming the diffusion barrier layer 170 and theseed layer 180, a process of forming the metal interconnection layer canbe performed to interconnect the layers.

Embodiments of the present invention can be applied to both singledamascene process and dual damascene process, and can be applied to theprocess for forming the contact hole and the via hole.

The semiconductor device and the method for manufacturing the sameaccording to the exemplary embodiment of the present invention canprevent an overhang from being generated due to a step difference of ahole in the process of forming a diffusion barrier layer and a seedlayer.

Further, according to embodiments of the present invention, theperformance degradation of the semiconductor device caused by anoverhang or a void can be prevented, so that the reliability of thesemiconductor device can be improved.

The embodiments and the accompanying, drawings illustrated and describedherein are intended to not limit the present invention, and it will beobvious to those skilled in the art that various changes, variations andmodifications can be made to the present invention without departingfrom the technical spirit of the invention.

1. A semiconductor device comprising: a semiconductor substrate having aconductive layer; an interlayer dielectric layer formed on thesemiconductor substrate, wherein the interlayer dielectric layer has ahole above the conductive layer, wherein an upper portion of the holehas a tapered angle; a diffusion barrier layer formed on the hole andthe interlayer dielectric layer; and a seed layer formed on the difusion barrier layer.
 2. The semiconductor device of claim 1, wherein alower portion of the hole has a width identical to a width of a middleportion of the hole, and a width of the upper portion of the hole iswider than the width of the lower portion of the hole.
 3. Thesemiconductor device of claim 1, wherein the diffusion barrier layercomprises a single TaN layer.
 4. The semiconductor device of claim 1,wherein the diffusion barrier layer comprises a single Ta layer.
 5. Thesemiconductor device of claim , wherein the diffusion barrier layercomprises a dual TaN/Ta layer.
 6. The semiconductor device of claim 1,wherein the upper portion of the hole is sunk at a predetermined angle.7. The semiconductor device of claim 1, wherein the upper portion of thehole has a width wider than the width of the lower portion of the hole.8. The semiconductor device of claim 1, wherein the lower portion of thehole has a width identical to a width of a middle portion of the hole.